Products
IOMMU
DuelSemi's IOMMU subsystem module is fully compliant with the RISC-V AlA architecture specification and the AXI4-Stream DTI interface. It supports configurable DID, PID, virtual address, physical address bit width, and various levels of translation cache sizes. It can be distributedly integrated into the SoC bus system. As the key building block, it enables heterogenous accelerator architectures and high performance networking/storage virtualizations in the cloud computing.
• Supports APB configuration interface
• Supports ACE5-Lite bus DMA access interface
• Supports ACE5-Lite bus page table/queue access interface
• Supports AXI4-DTI protocol interface
• Supports Svpbmt
• Supports Svnapot
• Supports Sv39/Sv48 S1 translation
• Supports Sv39x4/Sv48x4 S2 translation
• Supports S1+S2 nested translation
• Supports MSI flat translation
• Supports 20-bit DID
• Supports 16-bit PID
• Supports 48-bit DMA input address
• Supports PCle ATS
• Supports PCle PRI
• Supports PCle ATS T2GPA mode
• Supports configurable configuration cache, lookup table cache, and TLB size
• Supports externaly connected IOPMA and IOPMP modules independently developed by DuelSemi
