K1 is an octa-core 64-bit RISC-V AI CPU.

Based on RISC-V open instruction set architecture, we aim to create an energy efficient AI processor platform, promote global open source and open compute ecosystem. 

K1 is mainly used for single board computer, intelligent robots, various terminals running edge-side large models, home storage and computing terminals, industry computing terminals, AI PCs, edge node computers, and so on.

The PMIC (Power Management IC) P1 is a powerful solution. 

P1 is designed to meet the diverse power requirements of various applications. 

P1 is mainly used for AR/VR, industrial devices, AI Robots and drone.

DuelSemi's IOMMU subsystem module is fully compliant with the RISC-V AlA architecture specification and the AXI4-Stream DTI interface. It supports configurable DID, PID, virtual address, physical address bit width, and various levels of translation cache sizes. It can be distributedly integrated into the SoC bus system. As the key building block, it enables heterogenous accelerator architectures and high performance networking/storage virtualizations in the cloud computing.

DuelSemi's IOPMP module adheres to the RISC-V IOPMP architecture specification, adopts the Rapid-k model, supports configurable numbers of SIDs, Memory Domains, and Entries. Moreover, IOPMP can be flexibly integrated into SoC with either Source Enforcement or Destination Enforcement strategy, to achieve various security implementation. The lOPMP is optimized in frequency and designed to support different configurations. It is suitable for applications which require both security management and high performance, such as servers, intelligent computing chips and so on.

DuelSemi's AlA subsystem module is fully compliant with the RISC-V AlA architecture specification. It consists of the AlA CSRs and IMsiC within CPU core, and uncore APLIC module.It can be paired with the X1oo core to form a complete interrupt virtualization solution. The AlA CSRs are used to maintain the programming model introduced by AlA, IMSIC is responsible for receiving external MSl interrupts, and APLlC, as the external interrupt controller, forwards external interrupts to the RisC-V processor. The AlA subsystem can be used to implement interrupt virtualization, forming a complete virtualization solution.